畢業(yè)設(shè)計(jì) 基于FPGA的FIR數(shù)字濾波器的設(shè)計(jì)


基于FPGA的FIR數(shù)字濾波器的設(shè)計(jì)
摘要
在現(xiàn)代電子系統(tǒng)中，F(xiàn)IR數(shù)字濾波器以其良好的線性特性被廣泛使用，屬于數(shù)字信號(hào)處理的基本模塊之一。在工程實(shí)踐中，往往要求對(duì)信號(hào)處理要有實(shí)時(shí)性和靈活性，而己有的一些軟件和硬件實(shí)現(xiàn)方式則難以同時(shí)達(dá)到這兩方面的要求。隨著可編程邏輯器件和FDA技術(shù)的發(fā)展，使用FPGA來實(shí)現(xiàn)FIR濾波器，既具有實(shí)時(shí)性，又兼顧了一定的靈活性，越來越多的電子工程師采用FPGA器件來實(shí)現(xiàn)FIR濾波器。
本文對(duì)基于FPGA的FIR數(shù)字濾波器實(shí)現(xiàn)進(jìn)行了研究。主要工作如下:
(1)以FIR數(shù)字濾波器的基本理論為依據(jù)，使用分布式算法為濾波器的硬件實(shí)現(xiàn)算法，并對(duì)其進(jìn)行了詳細(xì)的討論。針對(duì)分布式算法中查找表規(guī)模過大的缺點(diǎn)，采用多塊查找表和OBC編碼方式使得硬件規(guī)模極大的減小。
(2)在設(shè)計(jì)中采用了層次化、模塊化的設(shè)計(jì)思想，將整個(gè)濾波器劃分為多個(gè)功能模塊，利用VHDL語言和原理圖輸入兩種設(shè)計(jì)技術(shù)進(jìn)行了各個(gè)功能模塊的設(shè)計(jì)，最終完成了FIR數(shù)字濾波器的系統(tǒng)設(shè)計(jì)。
(3)最后給出了采用FLEX10K系列器件實(shí)現(xiàn)一個(gè)16階的FIR低通濾波器的設(shè)計(jì)實(shí)例，用QuartusII軟件進(jìn)行了仿真，并對(duì)仿真結(jié)果進(jìn)行了分析，證明所設(shè)計(jì)的FIR數(shù)字濾波器功能正確。
仿真結(jié)果表明，本論文設(shè)計(jì)的濾波器硬件規(guī)模較小，采樣率達(dá)到了8.8MHz。同時(shí)只要將查找表進(jìn)行相應(yīng)的改動(dòng)，就能分別實(shí)現(xiàn)低通、高通、帶通FIR濾波器，體現(xiàn)了設(shè)計(jì)的靈活性。
關(guān)鍵詞：FIR數(shù)字濾波器；FPGA；分布式算法；OBC編碼；查找表
 

Design of the FIR Digital Filter Based on FPGA
Abstract
In the modern electrical system，the FIR digital filter is used form any practical applications for its good linear phase character, and it provide an important function in digital signal processing design. In engineering practice, there is always a real-time and flexible requirement for signal processing. However, software and hardware techniques available for implementation are difficult to meet the demand for the two aspects in the same time. Along with the development of PLD device and EDA technology, more and more electrical engineers use FPGA to implement FIR filter, as it not only meet the real-time requirement, but also has some flexibility.
In this paper, a method to implement the FIR filter using FPGA is proposed. The work mainly as follow:
(1) According to the basic theory of FIR filters, a scheme of hardware implementation is worked out using distributed arithmetic algorithm. As the scale of the LUT in the distributed arithmetic algorithm is so large, the thesis reduces it with the use of multiple coefficient memory banks.
(2) From the clew of implementing a top-down stratified, modular design, the thesis describes the hard ware design of all functional modules and the FIR system with the VHDL and schematic diagram design methods.
(3) At last, a sixteen-tapped low-pass FIR filter is taken as an example, and the simulation design carried out using QuartusII. And analyzed the result, and it proved that the function of the design is correct.
The result of the simulation indicates that the scale of the design is small, and the sample rate of the FIR filter can reach 8.8MHZ.Modifying the LUT can realize the low-pass, high-pass and band-pass FIR filters respectively, and incarnates the flexibility of the design.
Key words:FIR digital filter;FPGA;Distributed Arithmetic;Offset-Binary Coding；LUT

 
目錄
畢業(yè)設(shè)計(jì)（論文）任務(wù)書 I
摘要 II
Abstract III
第1章 緒論 1
1.1 本課題的研究意義和應(yīng)用背景 1
1.2 國(guó)內(nèi)外的研究現(xiàn)狀 1
1.3 研究思路 3
1.4 本論文的主要內(nèi)容和主要工作 4
第2章 FIR數(shù)字濾波器簡(jiǎn)介 5
2.1 FIR數(shù)字濾波器 5
2.1.1 數(shù)字濾波器的概述 5
2.1.2 FIR濾波器的原理 6
2.1.3 FIR濾波器的基本結(jié)構(gòu) 7
2.1.4 線性相位FIR數(shù)字濾波器的系統(tǒng)結(jié)構(gòu) 7
2.1.5 FIR數(shù)字濾波器的設(shè)計(jì)方法 8
2.2 實(shí)現(xiàn)FIR數(shù)字濾波器的硬件算法——分布式算法 9
2.2.1 分布式算法 9
2.2.2 分布式算法的優(yōu)化 12
第3章 EDA技術(shù)和可編程邏輯器件 17
3.1 EDA技術(shù) 18
3.2 EDA技術(shù)的主要內(nèi)容 18
3.2.1 大規(guī)?？删幊唐骷?nbsp;18
3.2.2 硬件描述語言VHDL 19
3.3 基于EDA技術(shù)的“自頂向下”的設(shè)計(jì)方法 21
3.4 基于EDA技術(shù)的電子電路設(shè)計(jì)流程 21
3.5 可編程邏輯器件 23
3.5.1 可編程邏輯器件簡(jiǎn)介 23
3.5.2 使用FPGA器件進(jìn)行開發(fā)的優(yōu)點(diǎn) 24
3.5.3 FPGA設(shè)計(jì)的開發(fā)流程 25
3.6 FLEX10K系列芯片介紹 26
3.6.1 FLEX10k的結(jié)構(gòu) 27
3.6.2 FLEX10K系列器件的特點(diǎn) 28
3.7 開發(fā)工具QuartusII介紹 28
第4章 FIR濾波器的設(shè)計(jì)與仿真 29
4.1 FIR濾波器的模塊劃分 29
4.1.1 濾波器模塊的劃分 29
4.1.2 方案確定 29
4.2 FIR濾波器各模塊功能的實(shí)現(xiàn) 30
4.2.1 控制模塊 30
4.2.2 輸入模塊 31
4.2.3 乘累加模塊 33
4.2.4 鎖存模塊 35
4.2.5 頂層設(shè)計(jì) 35
4.3 FIR數(shù)字濾波器的系統(tǒng)設(shè)計(jì) 36
4.4 FIR濾波器的綜合 39
4.4.1 數(shù)字系統(tǒng)綜合概述 39
4.4.2 本設(shè)計(jì)的綜合 39
4.5 FIR濾波器各模塊的仿真 41
4.5.1 控制模塊的仿真 41
4.5.2 輸入模塊時(shí)序仿真 42
4.5.3 乘累加模塊時(shí)序仿真 45
4.5.4 鎖存模塊時(shí)序仿真 48
第5章 結(jié)束語 51
5.1 總結(jié) 51
5.2 展望 51
參考文獻(xiàn) 53